CESE4095 System design with HDLs

Topics: VHDL language constructs and simulation/synthesis tools

As system design often requires the utilization of hardware description languages we concentrate on such a language, i.e., VHDL and their associated simulation and synthesis tools.

This course provides students with the required background to understand, modify, develop and debug VHDL system designs. Covered issues are related to VHDL language constructs as well as to the utilization of simulation and synthesis tools.

The addressed topics include among others the following: hardware modeling, simulation, and synthesis; behavioral and component descriptions; signals and entities; delay models; VHDL language constructs; basic I/O; identifiers, data types, and operators.


J.S.S.M. Wong

Last modified: 2022-06-19


Credits: 2 EC
Period: 2/0/0/0