[2025] A Rail-to-Rail EDO-Tolerant TDM Neural Recording Front-End for Large-Scale Implantable Brain-Computer Interfaces

Large-scale implantable brain-computer interfaces (BCIs) play a crucial role in advancing basic neuroscience research and clinical applications. Future implantable BCIs will greatly benefit from compact, low-power neural recording integrated circuits (ICs) with high channel counts. Time-division multiplexing (TDM) has emerged as a promising technique to enhance scalability by enabling multiple electrodes to share a single analog front-end (AFE), hence effectively reducing the per-channel area. However, existing TDM-based neural AFEs suffer from a critical challenge: their limited tolerance to electrode DC offset (EDO), typically <200mVpp. This limits their applicability, particularly when interfacing with small electrodes exhibiting large EDOs. Therefore, enhancing EDO tolerance in TDM-based neural AFEs, while maintaining other critical performance metrics such as area, power efficiency, and signal quality, is highly desirable.

References
[1] X. Huang et al., "Actively multiplexed µEcoG brain implant system with incremental-ΔΣ ADCs employing bulk-DACs," IEEE JSSC, 2022.
[2] U. Shin et al., "NeuralTree: A 256-channel 0.227-μJ/class versatile neural activity classification and closed-loop neuromodulation SoC," IEEE JSSC, 2022.
[3] N. S. K. Fathy et al., " A 0.00179 mm2/Ch chopper-stabilized TDMA neural recording system with dynamic EOV cancellation and predictive mixed-signal impedance boosting," IEEE TBCAS, 2024.
[4] X. Huang et al., "A 3072-channel neural readout IC with multiplexed two-step incremental-SAR conversion and bulk-DAC-based EDO compensation in 22nm FDSOI," in IEEE VLSI, 2024.

Assignment

The primary goals of this master’s thesis are to explore novel techniques for extending EDO tolerance, and develop a TDM-based neural AFE architecture that is capable of achieving the following key objectives:
1. Large EDO Tolerance: Enable (near) rail-to-tail EDO tolerance, overcoming the limitations of existing designs.
2. Ultra-Small Area: Achieve an effective per-channel area of <0.0004 mm², setting a new benchmark for miniaturization in neural AFEs.
3. Comparable Performance Metrics: Maintain essential specifications, including low power consumption (<1 μW/channel), low input-referred noise (<10 μVrms), low total harmonic distortion (<-40 dB), high input impedance (>20 MΩ), etc.
By achieving these objectives, this research aims to push the boundaries of state-of-the-art neural AFEs, advancing the development of compact, energy-efficient, large-scale implantable BCIs for fundamental neuroscience research and clinical neuroprosthetic applications.

Requirements

MSc student in Microelectronics with an interest in Analog/mixed signal IC design.

Required courses:

• Analog Circuit Design Fundamentals (EE4C10)

• Analog CMOS Design I (ET4295)]

• Nyquist-Rate Data Converters (ET4369)

• Analog IC Design (ET4252)

Contact

Last modified: 2025-03-10