[2024] Self-timed digital neural network hardware accelerators with event-driven clock generation

Neural networks, and especially event-based variants such as bio-inspired spiking neural networks, typically have a sparse activity. However, conventional digital hardware accelerators rely on an always-on clock, where the clock tree is known to take a significant part (30-50%) of the overall power budget. While clock gating partly mitigates this issue, applying it at a fine-grained level (e.g., on a per-neuron basis) leads to extra congestion overhead and increases the complexity of the clock tree, which in turns impedes proper timing closure and reduces performance.

In order to truly leverage the sparse activity of event-based neural networks for low-power edge AI, you will investigate emerging schemes for event-driven clock generation at a neuron level (e.g., see [1,2]). More specifically, you will:
- survey options for low-cost local clock generation and derive specifications,
- select a neural network architecture that can best exploit this strategy (co-design approach),
- design, and possibly tape out, your own chip based on the results of the steps above.

[1] https://www.frontiersin.org/articles/10.3389/fnins.2021.664208/full
[2] https://ieeexplore.ieee.org/abstract/document/9336139/

Requirements

You should be familiar with digital hardware description languages such as VHDL or Verilog, as well as with the digital IC design flow with tools such as Cadence Genus and Innovus.
You should also have basic notions of neural network training (if not, you can go through this excellent series of 4 videos: https://youtube.com/watch?v=aircAruvnKk&list=PLZHQObOWTQDNU6R1_67000Dx_ZCJB-3pi). Previous exposure to any deep learning framework (Keras, Tensorflow, PyTorch,...) is a plus.

This project will be in collaboration with SiTime, a world leader in precision timing. A 15-ECTS internship at their premises in Rijswijk is encouraged. SiTime offers financial support for tuition costs and encourages porting results to silicon with support for tapeout costs.

Interested students should send a motivation letter together with their CV (incl. course transcripts and grades) Dr. Charlotte Frenkel (c.frenkel@tudelft.nl).

More MSc proposals for Dr. Charlotte Frenkel will appear in the coming weeks, interested students are encouraged to reach out by e-mail to enquire about upcoming projects.

Contact

Last modified: 2024-02-06