MSc thesis project proposal
[Already taken] [2023] Massively Parallel Analog Front-End Array for Flexible CMOS-based Brain-Computer Interfaces
As the field of brain-computer interfaces (BCIs) continues to develop, the need for more channels to accurately capture neural signals becomes increasingly evident. Fully implantable wireless ASICs are needed to provide the necessary high-density recordings. However, ASICs are rigid, which can limit their potential for use in clinical settings.
This project focuses on developing a new architecture for flexible and scalable brain-computer interfaces (BCIs) that can still leverage the high integration of CMOS technology. The project aims to improve the performance of BCIs by massively increasing the number of electrodes used to record neural signals. The proposed architecture consists of a CMOS ASIC with an array of analog front-end (AFE) channels for high-density recording of neural signals. The ASIC will be designed to be compatible with post-processing techniques developed in another MSc project* to make silicon flexible so that the BCI system can conform to the brain. This project is an opportunity to be part of a groundbreaking research effort and contribute to developing a new architecture that could significantly impact the field of brain-computer interfaces.
This project is a collaboration between Dr. Filipe Cardoso (EI) and Dr. Dante Muratore (BE).
*partner project: https://ei.et.tudelft.nl/Education/thesisdetails.php?ti=586
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Assignment
The main objective of this project is to design an analog front-end array with 1000+ channels that can record local field potentials and is compatible with the stringent pixel area, power, and routing constraints of the post-processing steps for making the ASIC flexible. The project is embedded in ongoing efforts in the group for designing compact, ultra low power active digital pixels for BCIs. The project will involve the following specific objectives:
- Reviewing the existing literature on analog front-ends for BCIs, and identifying the key challenges associated with large channel count neural interfaces.
- Designing a low-power low-area analog front-end that is capable of recording local field potentials, and designing an array architecture that can easily scale to thousands of channels.
- Evaluating the performance of the proposed analog front-end array, by analyzing the quality of the recorded neural signals.
The proposed analog front-end will be designed in 40-nm CMOS technology using Cadence. The performance of the (manufactured*) analog front-end array will be evaluated in-vitro, and will be compared against existing state-of-the-art solutions.
*tapeout of the design is encouraged and supported, but not mandatory.
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Requirements
MSc EE-ME student.
You should be comfortable with mixed-signal IC design and the Cadence analog environment. Curiosity, hard work, and creativity are always needed. If you are interested, contact Dr. Dante Muratore via email with a motivation letter and attached CV (with taken courses and grades).
Prerequisites: EE4520 Analog CMOS design I, ET4369 Nyquist-rate data converters.
Recommended: ET4252 Analog integrated circuit design, ET4278 Over-sampled data converters.
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Contact
dr. Dante Muratore
Bioelectronics Group
Department of Microelectronics
Last modified: 2023-05-03
