MSc thesis project proposal
[2023] On-chip compression of action potentials for implantable brain-computer interfaces
The field of brain-computer interfaces has seen rapid growth in recent years, with a variety of implantable devices being developed for use in research and medical applications. These devices typically rely on recording electrical signals from the brain, which can then be decoded to control external devices or provide feedback to the user.
One major challenge in the development of implantable brain-computer interfaces is the large amount of data that must be transmitted wirelessly from the device to an external receiver. This data can be expensive in terms of power consumption, which is a critical consideration since implantable devices must operate for extended periods of time within the body.
On-chip compression of neural signals offers a potential solution to this challenge, by reducing the amount of data that must be transmitted without compromising the information content of the signals. This can be accomplished through the use of algorithms that identify and discard redundant or irrelevant information in the neural signals.
The goal of this MSc thesis project is to investigate on-chip compression of action potentials for implantable brain-computer interfaces. The project will involve designing and testing an algorithm for compressing neural signals without losing important information for decoding. In addition to designing an effective compression algorithm, it is important that the algorithm be low power and implemented on an ASIC for use in implantable devices. This will require careful consideration of hardware constraints and power consumption throughout the design process.
The resulting algorithm will be evaluated using both simulated and real neural data, with the ultimate goal of improving the performance and longevity of implantable brain-computer interfaces. Successful development of an on-chip compression algorithm could significantly improve the feasibility and scalability of implantable brain-computer interfaces, enabling new applications in research and medicine.
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Assignment
Deliverables:
- A working on-chip compression algorithm for action potentials in neural signals
- Evaluation of the algorithm using simulated and real neural data
- Evaluation of the power/area consumption of the chip after fabrication
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Requirements
MSc EE-ME, BME, EE-CE student.
You should be comfortable with Verilog/VHDL and the digital flow for IC design (synthesis and place&route using Synopsys/Innovus). Curiosity, hard work, and creativity are always needed. If you are interested, contact Dr. Dante Muratore via email with a motivation letter and attached CV (with taken courses and grades).
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Contact
dr. Dante Muratore
Bioelectronics Group
Department of Microelectronics
Last modified: 2023-05-28
